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74HC4024
7-stage binary ripple counter
Rev. 03 -- 12 November 2004 Product data sheet
1. General description
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024 of the 4000B series. The 74HC4024 is specified in compliance with JEDEC standard no. 7A. The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
2. Features
s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from -40 C to +80 C and from -40 C to +125 C.
3. Applications
s Frequency dividing circuits s Time delay circuits.
Philips Semiconductors
74HC4024
7-stage binary ripple counter
4. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. Symbol tPHL, tPLH fmax CI CPD
[1]
Parameter propagation delay CP to Q0
Conditions CL = 15 pF; VCC = 5 V
Min -
Typ 14 90 3.5 25
Max -
Unit ns MHz pF pF
maximum clock frequency CL = 15 pF; VCC = 5 V input capacitance power dissipation capacitance VI = GND to VCC
[1]
-
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs.
5. Ordering information
Table 2: Ordering information Package Temperature range 74HC4024N 74HC4024D 74HC4024DB 74HC4024PW -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C Name DIP14 SO14 SSOP14 TSSOP14 Description plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT27-1 SOT108-1 SOT337-1 SOT402-1 Type number
9397 750 13813
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Product data sheet
Rev. 03 -- 12 November 2004
2 of 18
Philips Semiconductors
74HC4024
7-stage binary ripple counter
6. Functional diagram
Q6 3 Q5 4
Q0 12 11 9 6 5 4 3
7-STAGE COUNTER
Q4 5 Q3 6 Q2 9 Q1 11 Q0 12
1
CP
Q1 Q2 Q3
2
MR
Q4 Q5 Q6
001aab906
CP 1
MR 2
001aab908
Fig 1. Functional diagram
Fig 2. Logic symbol
CTR7 0 1 + CT 2 CT = 0
12 11 9 6 5 4
6
001aab907
3
Fig 3. IEC logic symbol
Q CP T FF 1 T Q RD MR RD FF 2
Q T Q RD FF 3
Q T Q RD FF 4
Q T Q RD FF 5
Q T Q RD FF 6
Q T Q RD FF 7
Q
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
001aab909
Fig 4. Logic diagram
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
7. Pinning information
7.1 Pinning
CP MR Q6 Q5 Q4 Q3 GND
1 2 3 4 5 6 7
001aab905
14 VCC 13 n.c. 12 Q0
4024
11 Q1 10 n.c. 9 8 Q2 n.c.
Fig 5. Pin configuration
7.2 Pin description
Table 3: Symbol CP MR Q6 Q5 Q4 Q3 GND n.c. Q2 n.c. Q1 Q0 n.c. VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH) parallel output 6 parallel output 5 parallel output 4 parallel output 3 ground (0 V) not connected parallel output 2 not connected parallel output 1 parallel output 0 not connected positive supply voltage
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Product data sheet
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
8. Functional description
8.1 Function table
Table 4: Input MR H L CP X
[1] H = HIGH voltage level; L = LOW voltage level; X = don't care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition.
Function table [1] Output Qn L no change count
9. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC, IGND Tstg Ptot Parameter supply voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation DIP14 package SO14, SSOP14 and TSSOP14 packages
[1] [2]
[1] [2]
Conditions VI < -0.5 V or VI > VCC + 0.5 V VO < -0.5 V or VO > VCC + 0.5 V VO = -0.5 V to VCC + 0.5 V
Min -0.5 -65 -
Max +7 20 20 25 50 +150 750 500
Unit V mA mA mA mA C mW mW
Above 70 C: Ptot derates linearly with 12 mW/K. Above 70 C: Ptot derates linearly with 8 mW/K.
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74HC4024
7-stage binary ripple counter
10. Recommended operating conditions
Table 6: Symbol VCC VI VO tr, tf Recommended operating conditions Parameter supply voltage input voltage output voltage input rise and fall times VCC = 2.0 V except CP VCC = 4.5 V VCC = 6.0 V Tamb ambient temperature Conditions Min 2.0 0 0 -40 Typ 5.0 6.0 Max 6.0 VCC VCC 1000 500 400 +125 Unit V V V ns ns ns C
11. Static characteristics
Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Tamb = 25 C VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILI ICC CI VIH input leakage current quiescent supply current input capacitance HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
9397 750 13813
Parameter
Conditions
Min 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 1.5 3.15 4.2
Typ 1.2 2.4 3.2 0.8 2.1 2.8 2.0 4.5 6.0 4.32 5.81 0 0 0 0.15 0.16 3.5 -
Max 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8.0 -
Unit V V V V V V V V V V V V V V V V A A pF V V V
VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V
Tamb = -40 C to +85 C
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Product data sheet
Rev. 03 -- 12 November 2004
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
Table 7: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIL Parameter LOW-level input voltage Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILI ICC VIH input leakage current quiescent supply current HIGH-level input voltage VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILI ICC input leakage current quiescent supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0.1 0.1 0.1 0.4 0.4 1.0 160 V V V V V A A 1.9 4.4 5.9 3.7 5.2 V V V V V 1.5 3.15 4.2 0.1 0.1 0.1 0.33 0.33 1.0 80 0.5 1.35 1.8 V V V V V A A V V V V V V 1.9 4.4 5.9 3.84 5.34 V V V V V Min Typ Max 0.5 1.35 1.8 Unit V V V
Tamb = -40 C to +125 C
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Product data sheet
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74HC4024
7-stage binary ripple counter
12. Dynamic characteristics
Table 8: Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol tPHL, tPLH Parameter propagation delay CP to Q0 Conditions see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF propagation delay Qn to Qn+1 see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPHL propagation delay MR to Q0 see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTHL, tTLH output transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW CP clock pulse width HIGH or LOW see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR master reset pulse width HIGH see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trem removal time MR to CP see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum clock frequency see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance VI = GND to VCC
[1]
Min
Typ
Max
Unit
Tamb = 25 C 80 16 14 80 16 14 50 10 9 6.0 30 35 47 17 14 14 25 9 7 63 23 18 19 7 6 17 6 5 22 8 6 6 2 2 27 82 98 90 25 175 35 30 80 16 14 200 40 34 75 15 13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz pF
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Product data sheet
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
Table 8: Dynamic characteristics ...continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol tPHL, tPLH Parameter propagation delay CP to Q0 Conditions see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay Qn to Qn+1 see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPHL propagation delay MR to Q0 see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTHL, tTLH output transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW CP clock pulse width HIGH or LOW see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR master reset pulse width HIGH see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trem removal time MR to CP see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum clock frequency see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 4.8 24 28 MHz MHz MHz 65 13 11 ns ns ns 100 20 17 ns ns ns 100 20 17 ns ns ns 95 19 16 ns ns ns 250 50 43 ns ns ns 100 20 17 ns ns ns 220 44 37 ns ns ns Min Typ Max Unit Tamb = -40 C to +85 C
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
Table 8: Dynamic characteristics ...continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol tPHL, tPLH Parameter propagation delay CP to Q0 Conditions see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay Qn to Qn+1 see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPHL propagation delay MR to Q0 see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTHL, tTLH output transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW CP clock pulse width HIGH or LOW see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR master reset pulse width HIGH see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trem removal time MR to CP see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum clock frequency see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Min
Typ
Max
Unit
Tamb = -40 C to +125 C 120 24 20 120 24 20 75 15 13 4.0 20 24 265 53 45 120 24 20 300 60 51 110 22 19 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
13. Waveforms
MR input
VM tW trem 1/fmax VM tW
CP input
tPHL Q0 or Qn output
tPLH
tPHL VM
tTLH
tTHL
001aab910
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. VM = 0.5 x VI.
Fig 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency
VCC PULSE GENERATOR VI D.U.T. RT CL
mna101
VO
Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance.
Fig 7. Load circuitry for switching times Table 9: Supply VCC 2.0 V 4.5 V 6.0 V 5.0 V Test data Input VI VCC VCC VCC VCC tr, tf 6 ns 6 ns 6 ns 6 ns Load CL 50 pF 50 pF 50 pF 15 pF
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Product data sheet
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
14. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 14 8 MH wM (e 1)
pin 1 index E
1
7
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 8. Package outline SOT27-1 (DIP14)
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Product data sheet
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 pin 1 index Lp 1 e bp 7 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 9. Package outline SOT108-1 (SO14)
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Product data sheet
Rev. 03 -- 12 November 2004
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A X
c y HE vM A
Z 14 8
Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT337-1 (SSOP14)
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Product data sheet
Rev. 03 -- 12 November 2004
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 11. Package outline SOT402-1 (TSSOP14)
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Product data sheet
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Philips Semiconductors
74HC4024
7-stage binary ripple counter
15. Revision history
Table 10: Revision history Release date Data sheet status Change notice Doc. number Supersedes Document ID 74HC4024_3 Modifications:
20041112 Product data sheet
9397 750 13813 74HC_HCT4024_CNV_2
* * *
The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. Removed type number 74HCT4024. Inserted family specification. 74HC_HCT4024_1 -
74HC_HCT4024_CNV_2 19970901 Product specification 74HC_HCT4024_1 19901201 Product specification -
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74HC4024
7-stage binary ripple counter
16. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
18. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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Product data sheet
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74HC4024
7-stage binary ripple counter
20. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 November 2004 Document number: 9397 750 13813
Published in The Netherlands

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